Technical Field
The present disclosure relates to integrated circuit fabrication, and more specifically, to methods of controlling epitaxial growth over polysilicon-filled deep trenches for embedded dynamic random access memory (eDRAM), and the eDRAM so formed.
Related Art
Integrated circuit (IC) technology's continued advance toward ever smaller conductive line widths continually poses challenges. One current technology employs “14 nanometer” line widths (the widths are different for different structures; for instance, the fins are about 10 nm wide, and the gates, 20 nm) on semiconductor-on-insulator substrates. One structure in this technology that currently poses challenges during IC formation includes embedded dynamic random-access memory (eDRAM). In particular, each eDRAM includes a polysilicon-filled deep trench capacitor coupled to a respective finFET transistor. The polysilicon-filled deep trenches are formed in the substrate, and the transistors are formed above and also laterally adjacent to the deep trenches. As understood, each deep trench acts as a capacitor that provides a memory cell under control of the transistor coupled thereto.
Referring to FIGS. 1 and 2, partial formation of an example eDRAM 8 is illustrated in a plan view and a cross-sectional view, respectively. As shown in FIG. 1, transistors 10 are formed as fin type field effect transistors (finFETS), and thus include thin, closely spaced, semiconductor strips or “fins” 12 upon which gate conductors 14 are formed. Source/drain regions (not numbered) of transistors 10 are formed at ends of n-type transistor fin 12 as is polysilicon-filled deep trench capacitor 20. Deep trench capacitors 20 extend into the page in FIG. 1. As shown in FIG. 2, a drain region 22 of transistor 10 typically couples to polysilicon-filled deep trench capacitor 20 therebelow. During fabrication of the finFETS, as shown in FIG. 2, a thin layer of epitaxial silicon 24 is grown in drain region 22 over polysilicon-filled deep trench 20. As illustrated in FIG. 2, polysilicon-filled deep trench 20 may be recessed slightly prior to the epitaxy process. A challenge with formation of the eDRAM arises in that the growth or nucleation of epitaxial silicon 24 over the polysilicon of deep trench 20 can be more rapid and random than over just single-crystalline silicon (see random shape of epi silicon 24 in FIG. 1). In this situation, because fins 12 of transistors 10 are so closely spaced, epitaxial silicon 24 growth over polysilicon-filled deep trenches 20 causes deposited epitaxial silicon 24 to short deep trenches 20 and/or adjacent fins 12, i.e., electrically joining adjacent fins and/or trenches together and making the eDRAM inoperable. Potential short regions are shown in phantom ovals in FIGS. 1 and 2. The current situation leads to yield loss during eDRAM formation and limits the development of eDRAM at the 14 nanometer technology node and beyond.
A number of approaches have been proposed to solve the above-identified challenge. In one approach, implanting phosphorous into the fin has been proposed, but this approach adversely impacts device performance. Other proposals include: performing a longer and deeper recess of the drain region, but this has been shown to be ineffective at reducing deep trench shorts and increases strap resistance; performing an etch back of the polysilicon, but this requires additional masks after trench formation and several additional process steps; providing an oxide plug which increases strap resistance and negatively impacts device performance; and providing a deep trench collar, which also tends to increase resistance and slows read/write speeds for the eDRAM.